At HPE Discover 2026, the most interesting thing I found on the networking side was not a GPU. It was the tray feeding them: the HPE Juniper QFX5252, a scale-up switch carrying 204.8 terabits of capacity in a single liquid-cooled module for the AMD Helios AI rack.

Walking the floor on June 18 in Las Vegas, among the standard server racks and edge gateways, I stopped in front of the AMD Helios AI rack. It packs 72 AMD Instinct MI455X GPUs into one liquid-cooled scale-up domain. What caught my eye was not the compute. It was the cabling: thick yellow optical bundles cascading down both sides, the kind of cable plant that tells you the hard problem here is physical.

Key Takeaways

• HPE is showing the AMD Helios AI rack with a purpose-built HPE Juniper QFX5252 scale-up switch tray.
• Each tray runs two Broadcom Tomahawk 6 chips for 204.8 terabits of switching capacity.
• The design leans on a cable cartridge backplane and heavy external fiber bundles to reach that density.
• The real challenge for anyone deploying this is physical: optical routing, bend radius, and serviceability, not switch silicon.

Specs at a Glance

• Product: AMD Helios AI rack (HPE)
• Switch tray: HPE Juniper QFX5252
• Switch silicon: 2x Broadcom Tomahawk 6, 102.4T each
• Aggregate: 204.8 Tbps per tray
• Fabric: UALink over Ethernet (UALoE)
• OS: SONiC with AI-native operations
• GPUs per rack: 72x AMD Instinct MI455X
• Cooling: liquid-cooled

The Scale-Up Switch Tray Spec

The placard spells out the networking backbone for this rack.

The label confirms the move to UALink over Ethernet running SONiC, with each tray housing two Tomahawk 6 chips.

Front View and Cabling Realities

It looks clean under the booth lights, but the constraints are right there in the cabling.

The bundles bypass the central compute nodes entirely, which keeps the run clean but leaves little slack for anyone working in there later.

The Full Rack Context

Step back and the backplane design becomes the story.

Looking at the whole structure, the cartridge backplane is clearly there to carry a density that front-panel patching simply cannot support.

Floor Placement and Scale

A wide shot shows how much floor this footprint claims.

The cooling manifolds and power delivery stay out of sight, leaving only the primary networking and compute exposed to the aisle.

What I Could Not Confirm

The exterior optical routing is easy to read. What I could not see was how the quick-disconnects for the liquid-cooling loop sit behind the dense switch trays, which is exactly the part a service tech would want eyes on before the first move, add, or change.

Final Words

The placard lists two Tomahawk 6 chips at 102.4T each, so the tray carries 204.8 terabits of switching capacity in one scale-up module. If you see a larger number floating around, like 1,024, that is the accelerator count per pod, not the switching capacity of this tray. Worth keeping those straight.

At throughput like this, the bottleneck stops being silicon and becomes the cable plant. Look at the bend radius on those yellow exterior bundles. The whole thing depends on flawless optical routing, and the cartridge backplane exists precisely because front-panel patching cannot carry that density.

Here is my honest disclaimer: I do not rack AI superclusters. My world is production networks in live buildings, the kind with a wiring closet and a service window at 2am. But the physical layer does not care how many exaflops sit on top of it, and the questions are the same at every scale. Software failover covers a logical link going down. It does not cover a tech pinching a fiber on a side-run he cannot reach.

So the question I would ask before signing off on a rack like this: can your field techs safely pull a transceiver from a bundle this tight at 2am, in a cold aisle, without disturbing the links next to it?